Implementation of a High Speed Comparator for High Speed Automatic Test Equipment

نویسندگان
چکیده

برای دانلود رایگان متن کامل این مقاله و بیش از 32 میلیون مقاله دیگر ابتدا ثبت نام کنید

اگر عضو سایت هستید لطفا وارد حساب کاربری خود شوید

منابع مشابه

A High-Speed 64-Bit Binary Comparator

A high-speed 64-bit binary comparator is proposed in this brief. Comparison is most basic arithmetic operation that determines if one number is greater than, equal to, or less than the other number. Comparator is most fundamental component that performs comparison operation. This brief presents comparison of modified and existing 64-bit binary comparator designs concentrating on delay. Means so...

متن کامل

Design of A Novel High Speed Dynamic Comparator with Low Power Dissipation for High Speed ADCs

A new CMOS dynamic comparator using dual input single output differential amplifier as latch stage suitable for high speed analog-to-digital converters with High Speed, low power dissipation and immune to noise than the previous reported work is proposed. Back to-back inverter in the latch stage is replaced with dual-input single output differential amplifier. This topology completely removes t...

متن کامل

A Very High Speed, High Resolution Current Comparator Design

This paper, presents an idea for analog current comparison which compares input signal and reference currents with high speed and accuracy. Proposed circuit utilizes amplification properties of common gate configuration, where voltage variations of input current are amplified and a compared output voltage is developed. Cascaded inverter stages are used to generate final CMOS compatible output v...

متن کامل

A High Speed and Low Voltage Dynamic Comparator for ADCs

Abstract — A new dynamic comparator is proposed and it is compared with two existing comparators in terms of voltage, delay and frequency. CMOS dynamic comparator which has dual input, dual output inverter stage suitable for high speed ADCs with low voltage and low power dissipation. A conventional comparator is replaced with dynamic comparator which reduces the delay and voltage which increase...

متن کامل

A High-Speed CMOS Comparator for Use in an ADC

..-htracf —A high-speed CMOS comparator has been designed and fabricated using a standard 3pm process. A dynamic latch preceded by an offset-cancelled amplifier is used to obtain a response time of 43 ns. The offset-cancelled amplifier reduces the input-referred offset so that medium-resolution analog-to-digital converters (ADC’S) can be built with this comparator. The use of pipefining within ...

متن کامل

ذخیره در منابع من


  با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید

ژورنال

عنوان ژورنال: Journal of the Korea Industrial Information Systems Research

سال: 2014

ISSN: 1229-3741

DOI: 10.9723/jksiis.2014.19.3.001